The ever-present demand for the continual enrichment of consumer electronics and enterprise computing systems is often accompanied by demand to improve data storage capacity. The demand for greater storage capacity in turn stokes demand for greater storage density, so that specifications such as power consumption and form factor may be maintained and preferably reduced. Non-volatile memories, and flash memory in particular, are becoming increasing popular because they have enabled increased portability of consumer electronics, and more recently, have been utilized in relatively low power enterprise mass storage systems suitable for cloud computing and other mass storage applications. As such, there is additional pressure to increase the storage density of non-volatile memories, such as flash memory, in order to further take advantage of the beneficial attributes of such devices.
Semiconductor memory devices, including flash memory, typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A flash memory cell, for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value. Increases in storage density have been facilitated in various ways, including reducing the minimum feature size of semiconductor manufacturing processes in order to increase the number of transistors—and thus memory cells—that can be included in a particular area. Additionally, in order to further increase storage density, flash memory has developed from single-level flash memory to multi-level flash memory so that two or more bits can be stored by each memory cell.
A drawback of increasing storage density is that the stored data is increasingly prone to being stored and/or read erroneously. Error control coding (“ECC”) has been utilized to limit the number of uncorrectable errors that are introduced by pseudo-random fluctuations, defects in the storage medium, operating conditions, device history, and/or write-read circuitry, etc. Error control methods using soft information are particularly promising because soft information decoding may improve the error detection and correction capability of a particular error control code, and thus the capacity of the system. However, the utilization of soft information decoding has been limited because of a number of previously irresolvable drawbacks. For example, soft information decoding implementations tend to introduce undesirable delays, are generally power intensive and have relatively large semiconductor footprints. Consequently, the soft information decoding methods have remained relatively undesirable due to these and other physical constraints.